Research And Implementation Of High Speed Parallel Radar Signal Processing Algorithm Based On AI Accelerator Card

Deploying radars along the highway side is an imperative technology to guarantee the identification,detection,and track of the vehicles for the highway tolls.With the rapid development of highway and the continuous growth of traffic volume,some significant challenges are posed to achieve higher requirements in terms of the speed of radar signal processing,in order to realize the rapid and accurate recognition and detection of multiple targets.This dissertation,respectively,conducts the research and the simulation of the Fast Fourier Transform(FFT)algorithm and matrix Singular Value Decomposition(SVD)algorithm that are widely used in the process of radar signal processing based on the AI accelerator card.The high-speed parallelization operators of these two algorithms are designed and implemented by using the method of adapting the AI accelerator card.To be specific,for the high-speed parallel FFT operator,in this dissertation,firstly,it is studied that the realization method of the FFT on the AI accelerator card,and the python language is used for algorithm simulation and error statistics,which provides a theoretical guidance for the algorithm execution.Secondly,for the design and Implementation of the high-speed parallel FFT operator,two solutions are proposed based on the multi-core multi-threading technology and pipeline technology,and it is elaborated that the methods and steps to implement operators based on Ascend Computing Language(ACL)upon leveraging C/C++ programing language.Finally,it is given that the time-consuming trend of the two solutions in multi-core parallel computing,and it is compared and evaluated that the performance of the two solutions to achieve the operators on the AI accelerator card.More particularly,for FFT calculations of the same scale,when16 AI Cores are used,the multi-core multi-threading scheme and the two-stage pipeline scheme consume the least time and have the best performance.For the high-speed parallel matrix SVD operator,the matrix SVD is realized based on the power method.The python language is used to simulate the process of the algorithm implemented on the AI accelerator card.The calculation error is calculated and the iteration number of power method is determined by the calculation error,which provides parameters for development of the high-speed parallel matrix SVD operator.For the design and implementation of operators,in this dissertation,two schemes,i.e.,one-to-one and many-to-one,are proposed based on the power method,and it is clarified in detail that the method.By relying upon the ACL,C/C++ programing language is employed to realize the operator implementation.Finally,it is given that the total time-consuming trend and average time-consuming trend of the two solutions in multi-core parallel computing with the number of AI cores and the computing power of operators,and it is compared and evaluated that the performance of the two solutions to achieve the operators on the AI accelerator card.In the many-to-one scheme,when the matrices are merged diagonally according to 16 or its multiples,the time consumed of these schemes is better than others.In the case of the computing power with different requirements or that of computing with different numbers of AI cores,these schemes have their own advantages and disadvantages in terms of time-consuming performance and computing power.