Design Of Cap-less LDO Regulator With High PSR

Low-dropout regulator(LDO)are one of important parts of power management chips.It has the characteristics of simple structure,low power consumption and low noise,and can provide stable and clean dc voltage for the later load circuit.In recent years,the cap-less LDO has become a research hotspot because of its small size,no need of large external output capacitor and convenience for on-chip system integration.This paper introduces the working principle,circuit structure and parameter index of LDO,and designs a higher power supply rejection(PSR),fast transient response LDO circuit around the structure of cap-less LDO.In the LDO circuit,the power supply noise affects the output voltage through three paths.Path 1: noise through drain-bulk parasitic resistance and drain-bulk parasitic capacitance of the pass transistor.Path 2: noise through gate-source capacitance of the pass transistor.Path 3: noise through error amplifier.In order to improve the performance of PSR,it is necessary to reduce the output power noise of these three paths.For path 1,the output noise can be reduced by compensating its noise current.For the path 2,the output noise is reduced by increasing gate voltage and reducing gate-source voltage of the pass transistor.For path 3,the output noise is reduced by selecting the error amplifier with high PSR.Based on the discussion above,the LDO circuit with high PSR is designed in this paper.Firstly,the transient response enhancement circuit structure(TRE)is proposed as a solution to the problem of poor transient response cap-less LDO.TRE uses capacitance to detect ripple of the output voltage and feeds back to the current control structure of TRE to fast change the gate voltage of pass transistor.Finally,the pass transistor pulls the LDO output voltage back to the design value.Aiming at the stability problem,the miller compensation structure is used to separate the dominant pole and minor poles,so that the phase margin of the cap-less LDO circuit is greater than 60° and circuit reaches the stable state.To solve the problem of poor PSR of cap-less LDO at low frequency,five pipe op-amp is used and the noise voltage at the gate is equal to the noise voltage of the power source,and the output noises at the low frequency of the path 2 and path 3 are offset.For the problem of poor PSR at intermediate frequency,the circuit structure of PSR enhancer is proposed.The structure adopts the negative capacitance to offset coupling capacitance on gate-drain of the pass transistor,which makes the noise voltage at gate of pass transistor consistent with the noise voltage at source of pass transistor,reduces the power supply noise at the intermediate frequency of path 2,and improves the PSR performance of cap-less LDO circuit.Based on SMIC 0.18μm CMOS process,the proposed cap-less LDO regulator with high PSR is simulated and results show 87 m V of overshoot and 29 m V undershoot with 100μA-10 m A step load current when supply voltage is 1.2V,and the LDO achieves-75 d B PSR at 1MHz and the bandwidth of-3d B PSR is 1.5MHz at a load current of 10 m A.The quiescent current is 76.5μA.So the structure meets the design requirements.