Research And Design Of A Capacitor-less LDO With Fast Transient Response

With the rapid development of social science and technology and the diversification of electronic equipment,the integrated circuit industry is expanding increasingly.Almost all electronic equipment requires a power management system to ensure stable voltage.As one of the power management chips,the LDO regulator has the advantages of low cost,simple structure and superior performance,and it occupies an important position in the power management system.Traditional LDO circuits rely on off-chip large capacitors to maintain system stability,which increases chip cost and reduces chip integration,also polong down system response time.Now the chip is developing towards the So C concept,and the off-chip capacitance is no longer applicable in many fields.Therefore,how to improve the performance of on-chip integrated LDO without using off chip capacitors has become one of the research hotspots of power management chip technology in recent years.This thesis starts from the basic structure of LDO circuit,analyzes its working principle and performance indicators,and focuses on the stability and transient response of LDO.Comparing the stability of traditional LDO circuits and capacitor-less LDO circuits,because there is no buffering effect of large off-chip capacitors,when the load current changes abruptly,capacitor-less LDO circuits have no external devices to buffer the changes in stored charges and filtering,causing its output voltage to become unstable.In addition,the circuit structures are different,resulting in different main pole positions.The main pole position of the traditional LDO is located at the output end,and the main pole position of the capacitorless LDO is located at the output end of the error amplifier,and the position of the secondary pole of the output end will be changed with the load,which makes the compensation circuit of the capacitor-less LDO difficult to design.To solve the above problems,a capacitor-less LDO with enhanced transient response is proposed in this thesis.Combined with the basic structural framework,a bandgap reference voltage source circuit,an error amplifier,a power tube,and a compensation circuit are designed.In order to improve the temperature characteristics of the chip,the reference voltage source circuit has added high-level temperature compensation technology,which makes the temperature drift coefficient of the circuit significantly reduced;dynamic zero-pole tracking compensation circuit and the buffer circuit are adopted to increases the bandwidth of the system while ensuring the stability,and also improves the transient response performance of the circuit to a certain extent.In order to further enhance the transient response of the circuit,a transient enhancement circuit is improved and designed using the output voltage spike detection principle.By detecting the change of the output voltage of the LDO circuit,it responds to the gate of the power transistor to quickly charge and discharge to adjust the output current,thereby reducing the swooping and overshoot voltage of the output voltage.At the same time,to ensure the reliability of the chip,an over-temperature protection circuit is also designed to prevent the chip from being irreversibly damaged when it works in extreme environments.This work designs and simulates the proposed LDO circuit based on the SMIC 130 nm CMOS process,and completes the layout drawing and post-simulation analysis.The simulation results show that the input voltage range of the designed LDO circuit is 1.4～2.5V,the output voltage is stable at 1.2V,and the maximum load current of the circuit is30 m A.When the load current changes from 10μA to 30 m A within 1μs,the downshoot voltage generated at the output terminal is 48 m V,the overshoot voltage is 60 m V,and the response time is 1.4μs;when the frequency is 10 KHz,The power supply rejection ratio of the system is-64 d B under light load and-50 d B under heavy load.The quiescent current consumed by the system is 59μA.