Analysis And Design Of CMOS Low-dropout Linear Regulator

With the rapid development of electronic products in recent years, power management technology has become a popular research subject. In a variety of power management systems, low-dropout linear regulator(LDO) circuit is the most widely adopted one. The advancing technology and growing demand of the market, have made LDO with better transient response and fewer peripheral devices the research focus. Therefore, the research of LDO has significance in practice.In this paper, the basic principles and performance indicators of LDO are studied theoretically. The methods of improving the performance of key points of LDO are studied systematically. The analysis and discussion are focused on the reference voltage module, LDO frequency compensation scheme, LDO load transient response, LDO regulator core circuit and the protection circuit.Based on the above research and analysis, some improvements are made compared to the traditional LDO structure, a fast load transient response performance of capacitor-less LDO is designed based on SMIC 180 nm CMOS process. Theoretical analysis, design procedure and simulation process are also introduced. And the design process of key technologies and implementation methods are discussed in detail.Simulation results show that, when the input power supply voltage is 1.5 V, the output voltage is 1.2 V, the maximum load current is 300 mA. When the load current change between 1 mA and 300 mA with 1 μs, the maximum voltage overshoot is 62.3 mV, the transition response time is only 1.9 μs. Therefore, the LDO design enables fast load transient response with good overall performances.