Probabilistic Coverage Analysis Methods Using Markov Chains And Cross Coverage

Integrated circuit is one of the basic industries in the field of information technology.With the increase of the scale of IC design,functional verification as an important part of IC Verification,its difficulty is increasing day by day.When using excitation to perform functional verification,namely dynamic verification,coverage is the main method to measure the integrity of dynamic verification,that is,to measure the correctness of the design to be tested and control the dynamic verification process by the coverage.In practice,when the coverage rate reaches a certain coverage standard,the test stops.However,the test can only expose bug,but can not prove whether the bug exists,which is called the bug existence problem.In recent years,research on this problem has been carried out,that is,to calculate the probability of the next undetected bug under current test process based on Bayesian theorem,which is called probabilistic coverage analysis method.Probabilistic coverage analysis method is a supplement to coverage analysis method,which can help to measure the completeness of verification,and improve the current dynamic verification process.However,the current probabilistic coverage analysis methods are not perfect,such as only for combinational circuits or sequential circuits,and the accuracy and efficiency are not high enough.Therefore,further study on the probabilistic coverage analysis method is needed to achieve a higher level of accuracy and efficiency.The main work of this thesis is as follows:This thesis introduces the research background of probabilistic coverage analysis method and its research status.This thesis studied the probabilistic coverage analysis method based on cross coverage and Markov chains.Firstly,the probabilistic coverage analysis method for combinational logic circuits is proposed when using random,polling and hybrid strategies to select cross coverage bin for functional verification.Secondly,a probabilistic coverage analysis method is proposed for sequential logic circuits when random excitation is used for function verification.Finally,the proposed probabilistic coverage analysis method is verified.The main innovation of this thesis is to model the test process of sequential logic circuit using random excitation based on Markov chain.Specifically,the state of sequential logic circuit in the test is marked with the probability of exposing bug,and the state space is simplified,and the corresponding transition direction and transition probability are marked.Based on the above model,a formula is given to calculate the probability of bug detection after several random tests,and the formula is compared with the corresponding algorithm in exist paper in terms of accuracy and efficiency.The experimental result shows that the relative error of the results is reduced from 7.38%to 0.027%,the running time is shortened from 0.3s to 0.007 s when the number of states is 100 and the number of tests is 10000,and the running time is shortened from 1800 s to 284 s when the number of states is 20000 and the number of tests is 10000.The experimental result shows that the formula has higher accuracy and efficiency.