Coverage metrics for hierarchical validation of complex behavioral hardware designs

Hierarchical verification requires the verification of individual components followed by the verification of the interactions between components. Since the functionality of a complex system is divided into several subcomponents, it is important to verify each component's correctness and communication among those components to verify the whole system's correctness. Verifying each individual subcomponent (unit verification) alone is not sufficient to prove correctness of the system as a whole. This crisis is more significant when some subcomponents are Intellectual Property (IPs) whose implementation details are completely hidden. IP components are guaranteed to be correct in isolation so unit verification is not needed. However, a misunderstanding of the specification can still result in system errors in the IP's interaction with the other system components. For these reasons there is a great need to verify interactions among different components as well as individual components in the design. Validation using simulation requires the development of a test sequence which can reveal design errors that may be present. Test generation may be performed automatically or manually, but in either case there is a strong need for an empirical measure of the effectiveness of a test sequence. A measure of test effectiveness is referred to as a Coverage Metric that acts as a completion criterion for the test generation process.; I have implemented a Control-flow Oriented Coverage Metric (CoCM) to validate a single process (unit verification) in the design. CoCM metric tries to explore all feasible control flow paths while pruning infeasible interactions in a given process. In addition to the CoCM metric, a Interaction Coverage Metric (ICM) has been developed to verify communication among multiple processes. ICM metric uses data dependency and constraint solving techniques for pruning infeasible interactions across multiple processes and thereby making the integration verification more practical. Combination of these two metrics should alleviate problems involved in verifying a complex hardware system involving multiple processes.