FPGA Implementation Of GPS Acquisition System And Its Veriifcation Technology

With the increasing demand for GPS products and the rapid development of ICdesign technology, more and more companies are engaged in ASIC productdevelopment and application of GPS. To construct a universal GPS signal processingsystem and its verification platform will reduce the time on product design andfunctional verification. This thesis mainly focuses on the GPS acquisition algorithm andits hardware implementation technology. A hierarchical, reusable, coverage statisticstestbench is built.At present, the traditional time domain related acquisition method is adopted inmost cases. It requires a lot of hardware resources and has poor real-time performance.If correlation calculation of the N points in the time domain is transformed into thefrequency domain using FFT parallel acquisition method, only N times multiplication isneeded on the search of all CA code phase in a carrier frequency. The average samplingtechniques is proposed in this thesis to improved FFT parallel acquisition method. IFdata will be sampled into1024points without affecting the performance of theacquisition, and the premise ultimately simplify the hardware implementation process.Matlab simulation of FFT parallel acquisition method and the improved FFT parallelacquisition method is realized after generating5000points GPS IF sampling signal.FPGA design of the improved method is completed using Verilog. The results show thatthe improved FFT parallel acquisition method can achieve capture function and has alow utilization rate of hardware resources. The hardware implementation is simplified.On improved FPGA design, the verification of acquisition part needs1000testcases at least. The verification of HDLC module needs13test cases. If manually written,it is a huge amount of work. Test cases cannot be reused and results contrast is alsoexhausted. In this thesis, hierarchical verification platform is constructed using SystemVerilog. It could realize the reuse of verification components reducing the relevance ofthem.8verification components could generate a large number of test cases and achieveautomatically comparisons with output signal. Test cases number will be greatlyreduced. Using code coverage, functional coverage, assertion coverage statistics, testresults will be collected and analyzed. Fully verification will be achieved.