Large-point FFT Accelerates Ip Design And Verification

Modern digital signal processing technology is is applied in the work scenes with high data traffic interaction such as large-scale and complex real-time image processing,high-density and large-scale voice signal processing,radar signal technology.Each field requires the system equipped with high-efficiency and low delay real-time processing ability needs the hardware performance to keep up.With the increasing scale of chip design and the increasing difficulty of design,various challenges emerge in endlessly,and the time to market is relatively short.While encouraging the integration of So C designed IP cores,large-scale So C inevitably puts forward higher requirements for IP reusability,professionalism and fast integration,which brings a huge demand for the development of IP kernel applied in various professional scenarios.As an indispensable processing method in the field of digital signal processing,fast Fourier transform can improve the processing efficiency of the system,reduce the power consumption of the equipment and the delay waiting time of the system.Therefore,it is of great market application value to study FFT which has high performance,high precision,low delay and is easy to realize in engineering.Firstly,this article discusses the principles and characteristics of various algorithms that are currently commonly used to implement FFT operations,makes an in-depth analysis of several fixed-radix-2~n implementation principles of the classical CTA algorithm,summarizing the operation rules of one-dimensional fixed-radix-2algorithm and one-dimensional fixed-radix-4 algorithm.According to the specific requirements of the project,the one-dimension fixed-radix-2/8 butterfly operation in CTA algorithm was selected as the key step of FFT solution.This thesis studies the commonly used FFT computing hardware architecture:architectures that based on pipeline structure,memory structure,parallel structure,array structure,etc.and analyzes the computing characteristics of one-dimensional fixed-radix-2 algorithm SDF/MDC pipeline structure in detail.The hardware multiplexing structure based on memory and address conflict-free design is selected and realized by fully considering the factors such as accelerator computing performance and occupying resources.Then,the key parts of the operation realization,including storage control module,butterfly operation module,operand/result number address conflict-free storage rule,storage module based on the rotation factor compression algorithm,address generation module of operand/result number/rotation factor,and IFFT operation realization principle,are designed and explained in detail.Finally,the test and verification of the RTL code was completed.Under the operating frequency of 400Mhz,the software simulation results showed that the operating time of the maximum 32K point was51.63?s,and the function was correct within the allowable error range.At the same time,the software and hardware joint verification was carried out by means of FPGA.The experimental data showed that the actual execution cycles of the hardware were consistent with the software results,which ensured the reliability and accuracy of the design results.By flexibly configuring the design of 1K,2K,4K,8K,16K,and 32K points FFT operation,it fully meets the requirement of completing a 32K point FFT/IFFT operation within 80?s under the operating frequency of 400MHz,which lays a foundation for efficient reuse of computing IP,shortening the research and development cycle of processors,and helping to solve the hardware acceleration problems in the fields of signal and information processing.