Design And Hardware Implementation Of High-speed Mixed-radix FFT Processor

In real-time signal processing systems,the Fast Fourier Transform algorithm(FFT)is widely used because it can significantly accelerate the calculation process of the discrete Fourier transform.After a long period of development,the FFT algorithm has a variety of implementation forms,applied to different scenarios.Most application scenarios require the FFT processor to have high throughput and high real-time performance,so it is of great practical significance and application value to study a high-performance FFT processor.Based on the task characteristics of multi-sequence length calculation and longsequence calculation,this thesis deeply studies different FFT algorithms,implementation structure and factors that affect the performance of the processor.On the basis of the above work,a high-performance FFT processor with a mixed structure of radix-2 FFT algorithm and radix-8 FFT algorithm is designed.Xilinx Virtex7 2000 T FPGA is used to build a verification environment for the platform,and complete logic synthesis and backend implementation in SMIC 40 nm process and TSMC 28 nm process respectively.The simulation and verification results show that all functions of the FFT processor designed in this paper are correct and meet the project design goals.The main research work of this thesis: 1.Research and analyze the classification and principle of various FFT algorithms,summarize and compare the complexity,operation amount and implementation of the algorithms,and choose the radix-2 FFT algorithm and the radix-8 FFT algorithm as the implementation algorithm.Summarize the advantages and disadvantages of the four commonly used FFT processor architectures,and combine the advantages of sequential recursion and parallel iteration architecture to design the FFT processor architecture.2.The reconfigurable butterfly operator designed in this thesis is compatible with 8-channel parallel radix-2 FFT and single-channel radix-8 FFT algorithms,and can complete the calculation mode switching according to the configuration information.The conflict-free rules of radix-2 FFT algorithm and radix-8 FFT algorithm are designed to solve the problem that the butterfly calculation pipeline is suspended due to the excessive reading and writing bandwidth of the multi-channel parallel butterfly calculator.Optimize the implementation method of the rotation factor compression algorithm to ensure the compression efficiency while meeting different FFT calculation needs.3.This thesis completes the hardware test verification of the FFT processor on Xilinx XC7V2000 T FPGA.From the verification results,the designed FFT processor supports 32-bit single-precision floating-point FFT / IFFT calculation,and the calculation sequence length is 1K-32 K,the average error is 10.The thesis also completed the logic synthesis and back-end implementation of SMIC 40 nm process and TSMC 28 nm process.The layout report shows that the performance of the designed FFT processor meets the expected requirements.