| In manufacturing VLSI circuits, process-induced variations in device characteristics can drastically reduce the yield of fabricated chips. For submicron devices, small perturbations in the process input parameters will translate into drastic reductions in the number of operational chips. Understanding the relationships between the process inputs, device characteristics and device variabilities has therefore become a critical issue in VLSI fabrication. Obtaining such statistical information by running a large number of wafers through a fabrication line is too costly, time-consuming and complex. Technology computer-aided design (TCAD) tools simulate the fabrication process and the electrical properties of the devices. In this work we discuss a statistical simulation strategy for estimating VLSI device variabilities. A statistical simulation program has been developed to automate the task of physical simulation and perform the statistical analysis. In this thesis, the results of an extensive investigation of the statistical techniques for VLSI TCAD will be presented. The topics which will be discussed are response surface methodology and a Bayesian approach for design and analysis of computer experiments. The application of these statistical techniques to the design of VLSI technologies will also be demonstrated. |
