| Oversampled sigma-delta conversion has received increasing attention as a candidate for high resolution analog-to-digital (A/D) and digital-to-analog (D/A) conversion because it is robust against circuit imperfections and well suited for VLSI implementation. This thesis is an effort to provide a theoretical basis for oversampled analog-to-digital conversion. Here, unlike most traditional analysis, the nonlinear difference equations describing the system are solved exactly without any linearization approximations. The quantization noise in classical single-stage and more recent multi-stage sigma-delta modulator is analyzed, and the improvement in signal-to-noise ratio with oversampling ratio and number of stages is quantified. A quasi-stationary process model is proposed for input signals in order to study the quantization noise from an oversampled modulator resulting from deterministic and random inputs. In particular, dithering and its effects on sigma-delta and multi-stage sigma-delta modulation are studied in detail. We also investigate modulo sigma-delta modulation, which has a modulo limiter as a precoder to compress the input into the no-overload range of the system. The implementation issue of multi-stage oversampled A/D conversion is considered, and a time-sharing multi-stage sigma-delta modulator (TMSM) is proposed to eliminate the gain mismatch problem in multi-stage systems. |
