| Analog-to-digital (A/D) converters are a critical part of wireless receivers. High performance data converters reduce the complexity and cost of the analog part of a receiver and enable the aggressive utilization of digital signal processing. Such applications place increasingly severe demands on the speed and bandwidth of the A/D converters. However, A/D converters are typically adapted to one of these two requirements, either high speed or high precision.; Oversampled A/D converters are well suited for high-precision, low-speed applications such as audio signal processing. This dissertation proposes two approaches to adapting oversampled A/D converters to higher speed applications. In one architecture a large signal bandwidth is obtained through the use of a dual-quantization topology that achieves performance comparable to a cascade architecture with multibit quantization. A second approach introduces a noise shaping technique to improve the quantization noise suppression in cascaded modulators at low oversampling ratios.; Experimental modulators based on the proposed architectures have been designed and implemented in a 0.25-μm CMOS technology. The design employing dual quantization is a two-path, sixth-order, switched-capacitor sigma-delta modulator capable of digitizing a 1.25-MHz signal band centered at an IF of 20 MHz. This modulator samples the input at 80 MHz and implements its constituent resonators by first chopping the signal at the IF ( fs/4). The experimental prototype of this modulator provides a dynamic range of 80 dB when operated from a single 2.5-V supply with 90 mW power dissipation.; In a modulator employing extended noise shaping, the center frequency of the third stage in a three-stage cascade is shifted from that of the first two stages to achieve more efficient noise shaping across the signal band. The experimental prototype of this design achieves a dynamic range of 75 dB with a maximum SNDR of 70 dB when digitizing a 2-MHz signal band centered at 16 MHz. This circuit implements an fs/4 bandpass architecture and thus operates at 64-MHz clock rate. It dissipates 110mW from a 2.5-V supply. |
