Deterministic execution time prediction of programs/tasks on the i860 architecture

Accurate execution time information of a Task/Program can be used by a Scheduler to schedule the tasks onto the processes of the underlying architecture to minimize the total completion time of the application program.;Instruction times in contemporary computers seem notoriously nondeterministic (unpredictable) due to the complex-performance enhancements features such as cache memories and pipelining.;Several compile-time and run-time techniques have been studied. But, they do not account for the cache and pipeline features present in the underlying architecture.;The goal is to develop and design a model for predicting the deterministic behavior of programs coded in higher level language.;This is further used in the development of the Architecture Specification Tool for the PARSA (PARallel program Scheduling and Assesment tool) environment, the i860 processor.;This is further used in the development of the Architecture Specification Tool for the PARSA (PARallel program Scheduling and Assesment tool) environment, the i860 processor being considered as the target architecture. Hence, efficient scheduling and allocation of tasks onto the target architecture can be made possible using the PARSA tool.