| Performance in analog circuits is often critically linked to the physical implementation and the technology used for fabrication. While for digital circuits several synthesis techniques have been proposed and are of common use, in the analog domain, most of the high performing systems and chips are designed largely by hand.;In this prospective we have proposed a methodology for the semi-automated synthesis of full-custom analog IC layout at medium to high frequencies. The methodology guarantees that all performance constraints be met when feasible, otherwise infeasibility is detected as soon as possible, thus providing a robust and efficient design environment. In the proposed approach, performance specifications are translated into lower-level bounds on parasitics or geometric parameters, using sensitivity analysis. Bounds can be used by a set of specialized layout tools performing stack generation, placement, routing, compaction and extraction. For each tool, a detailed description is provided of its functionality, of the way constraints are mapped and enforced, and of its impact on the design flow.;A major advantage of the methodology is the reduction of time-consuming redesign loops often needed in purely bottom-up approaches, provided that accurate models for all relevant parasitics are available. For this reason, a wide variety of compact and highly sophisticated parasitic models has been generated to cover a sufficiently wide frequency spectrum. The effects of currents generated by high-speed digital switching circuits and the mechanisms governing noise injection have also been modeled and used to drive the design towards viable solutions.;A considerable number of examples drawn from industrial applications has been generated and fabricated in various technologies to illustrate the effectiveness of the approach. |
