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Topological optimization for VLSI layout design

Posted on:1998-12-06Degree:Ph.DType:Thesis
University:Northwestern UniversityCandidate:Chen, Hsiao-Feng StevenFull Text:PDF
GTID:2468390014975982Subject:Computer Science
Abstract/Summary:
ome VLSI layout problems related to the topological optimization are studied in this thesis. Firstly, we consider the problem of transforming a single-layer topological routing of n two-terminal nets into a rubber-band equivalent using rectilinear wires. Given a topological planar VLSI layout sketch with...
Keywords/Search Tags:VLSI layout, Topological
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