| During recent years the intense drive for signal integrity has been at the forefront of rapid and new developments in CAD algorithms focussed on microelectronics. As signal frequencies are approaching the GHz range, the interconnect effects such as delay, crosstalk, ringing and distortion become the dominant factors limiting the overall performance of VLSI systems. At relatively higher frequencies, interconnects can no longer be treated as lumped components; instead distributed, full-wave and measured models become necessary. However, simulation of large number of interconnects with high-frequency models using conventional simulators such as SPICE becomes prohibitively CPU expensive and also suffers from mixed frequency/time difficulties. Recently, several model-reduction algorithms, such as asymptotic waveform evaluation (AWE) and complex frequency hopping (CFH) have been introduced to enable rapid simulation of large interconnect networks. However, in the case of multiport subnetworks, the macromodels obtained using these techniques become inefficient for the purpose of nonlinear simulation. In addition, the reduction algorithms available in the literature can neither handle full-wave and measured subnetworks efficiently nor guarantee the passivity of reduced-order models for such networks.; In this thesis, a novel algorithm is presented for efficient model-reduction of multiport interconnect subnetworks. The proposed technique enables the generation of time-domain macromodels: with fewer states and facilitates efficient simulation of large interconnect networks in the presence of nonlinear elements. In addition, a new scheme to preserve the passivity of macromodels is presented to ensure stable nonlinear simulation. Also new techniques for simulation of full-wave and measured subnetworks using model-reduction algorithms are described. The proposed algorithm provides 1–3 orders of speed up compared to SPICE and is useful for accurate and efficient transient response estimation involving linear subnetworks in VLSI chip packaging, multi chip modules, printed circuit boards and in VLSI systems design. |
