Real time image processing on parallel arrays for gigascale integration

Portable multimedia systems require high performance, high efficiency, and the ability to exploit future gigascale VLSI technology. Limits of fixture on-chip interconnect, as projected in the National Technology Roadmap for Semiconductors (NTRS), increase communication costs and prevent the scaling of existing architectural approaches. New architectures must better exploit physical data locality to reduce the demand on global interconnects. This dissertation presents a system-level approach to localize computation and communication in an efficient computing platform. Research contributions include system models that capture interconnect-demand and describe architectures in gigascale technologies, and systolic synthesis procedures to map algorithms for area I/O arrays using planar streams. The system models average 60% more accurate in predictions of wire demand than existing stochastic models. A new area I/O systolic architecture is presented to exploit the physical locality of planar data streams by processing the data where it falls. New synthesis procedures for planar data streams presented in this thesis provide a three times increase in performance over previous techniques. Simulation results show that area I/O can provide additional average speedups of 16 times by exploiting additional data parallelism. This systolic array is approximately two orders of magnitude more area and power efficient than DSP and general-purpose microprocessors.