A generic system simulator with novel on-chip cache and throughput models for gigascale integration

Future opportunities of gigascale integration are governed by a hierarchy of limits of which system limits are the most numerous, constraining, and difficult to define. A generic system simulator, GENESYS, is proposed as the most promising approach to identifying future system limits and opportunities. The GENESYS analysis tool assimilates the entire hierarchical description of a chip through a concise set of input parameters and projects its key performance metrics by engaging a set of interrelated models incorporating both physical principles and empirical knowledge. This research enables simultaneous consideration of both the implementation technology and architecture of future microprocessors through the unique integration of phenomena from each level of the hierarchy as well as the utilization of novel cycle time, generic on-chip memory, and instructions-per-cycle models.; GENESYS and its core models are verified by simulating commercial microprocessors and comparing the predictions with the actual areas, power dissipations, and throughputs. Based on the technology and integration levels projected by the National Technology Roadmap for Semiconductors (NTRS) and optimal multi-level interconnect architectures and memory hierarchies identified by GENESYS, throughput is projected across the NTRS roadmap. Simulations indicate that the clock frequency and throughput become limited by global interconnects after 2006. For a given technology, GENESYS identifies the optimal zone of synchrony at which throughput reaches a maximum. Cellular array architectures or alternative novel architectures that ensure short wires will be required to sustain current rates of performance growth.; This dissertation provides the first systematic approach to predicting the throughput of gigascale integration systems and elucidates the tradeoffs and physical limits as well as the opportunities of these systems.