Circuit design and modeling of ferroelectric memories

This thesis explores three areas of research in ferroelectric memories: behavioral modeling of ferroelectric capacitors, circuit design, and architecture.;We propose a behavioral macromodel for ferroelectric capacitors that can be integrated into HSPICE for both small-signal and large-signal circuit simulations. The proposed model relies on both hysteresis loop and pulse measurements of the capacitor. We demonstrate the accuracy of the model by predicting the bitline voltage in a ferroelectric memory array testchip. We use the model, in conjunction with HSPICE, to verify the functionality of our proposed circuits throughout this thesis.;We propose a new reference generation scheme, for a 1T-1C ferroelectric memory architecture, that is less sensitive to device imperfections of the ferroelectric capacitors. The proposed scheme uses reference current signal, instead of reference voltage, for higher linearity and accuracy.;We propose new architectures for both binary and multiple-valued Ferroelectric Content-Addressable Memories (FCAM). We provide detailed circuit-level designs for these architectures, and evaluate their performance by circuit simulations. The proposed multiple-valued architectures can be searched not only for a stored data item that is equal to the reference data, but also for stored data that is either greater-than or less-than the reference data. All proposed architectures offer nonvolatile storage with a real-time programming feature suitable for write-intensive applications.