| This thesis examines the feasibility of developing an ATM simulator to help in the research and teaching of 25.6 Mbps ATM networks. An ATM chip has been successfully developed to perform the ATM layer's functions for the ATM simulator in this thesis. This chip consists of nine function blocks plus three FIFOs. These function blocks include three interfaces: PCI bus, UTOPIA and SRAM interface, five function modules: cell capture, cell delay, cell insert, error generation, and control utility, and one testbench block built inside the chip to simulate the physical chip connected to the UTOPIA interface. This ATM chip has been implemented into a Xilinx FPGA: XC4062XLA and tested on a PCI-based prototyping board. It runs at a clock rate of 33MHz. Total used size of the chip is 1665 CLBs (about 70K gates). In addition, a Win98 C++ application program has been developed to test this chip. |
