Research On Reduced - Order Method Of Trajectory Piecewise Linear Model For Nonlinear Circuit

With the increasing complexity of very large scale integrated circuits(VLSI), simulation and verification of integrated circuits have already become the key step in IC design flow. Model order reduction(MOR) is a effective technique in analysis of large-scale circuit systems, which can reduce the complexity of large-scale models, so as to enhance the efficiency of simulation and verifacation. Large amount of work was committed to MOR techniques of linear time invariant systems in the last decades, however MOR technique of nonlinear systems remains a major challenge. The current standard MOR method of nonlinear circuirs is Trajectory Piecewise Linear(TPWL) MOR technique, which has already been applied in many fields such as simulation of IC and biochemical systems. TPWL approximates nonlinear systems with piecewise linear models,and reduces the orders of each linearized models based on projection reduction method. In this thesis, major scientific problems of TPWL are studied. First, how to effectively approximate the nonlinear system with piecewise linear models, and second, how to reduced the linearizations to guarantee accuracy and the reduced orders.In the first step of TPWL-MOR method, the nonlinear system is approximated with piecewise-linear models. Very large scale nonlinear systems have high-dimensional state spaces. For strongly nonlinear systems, in order to guarantee the accuracy of the piecewise-linear models, a large number of expansion state poins must be extracted to cover the whole regions where state vectors are possible to reach.The will lead to large number of linearized models, large scale models and long simulation time.In this thesis, a Subspace-TPWL-MOR model is proposed which can be proved to increase equivalent expansion points coverage in state space, by sampling expansion points in subspaces of the full state space. Therefore, subspace TPWL model can greatly reduce the number of expansion points, and meantime increase the preciseness of the models. Furthermore, the simulation time can be dramatically reduced due to smaller model sizes. The subspace TPWL MOR method has two branches."Circuit-level" subspace TPWL-MOR method is proposed for module-based circuit systems, in which each module is reduced with Port-Preserving MOR method, so that the reduced-order models(ROM) of each modules can be reused, and the ROM of top-level circuit can is achieved by multi-instantiations of the ROM of modules. On the other hand,"System-level" subspace TPWL MOR method is proposed for circuits which are not module-based, in which an efficient partition algorithm is proposed to divide a circuit into multi-subspaces, and TPWL-MOR method can be applied to the partitions. Both "circuit-level" and "system-level" subspace TPWL MOR methods can be combined to further reduce the complexity of the VLSI models.In the second major step of conventional TPWL-MOR method, each linearizations are reduced with a global projection space, which is built by merging all projection spaces of all linearizations. If the number of expansion points is large, the merged projection space will be large, which will lead to a large reduced order.In this thesis, a fast MOR model with localized reductions and global interploation is proposed. In this fast MOR model, each linearization has a distinct projection matrix, which is built from only projection space of one linearization, therefore the reduced order can be extremely small. To solve the problem of inconsistent projection spaces, a orthogonal transformation is applied to minimize distances between two reduction spaces, so that reduced order models can be compared directly. Numerical experiments show that the proposed fast model not only can largely reduce the complexity of the model, but also can greatly improve the simulation speed.