Design for ESD reliability in high-frequency mixed-signal integrated circuits

Electrical overstress (EOS) and electrostatic discharge (ESD) pose the most dominant threats to integrated circuits (ICs). Industry surveys indicate that nearly 40% of all IC failures are attributed to EOS/ESD events. To analyze the typical damage of an ESD event, three primary models have been developed. In particular, charged device model (CDM) is a rapidly growing threat as electronic components increasingly rely on automatic handling equipment.; In this thesis, we first address CDM modeling and simulation issues. The difficulties of CDM simulation mainly result from the (1) high speed and high current characteristics of CDM waveform and (2) modeling of on-chip parasitic components. We have proposed a new methodology to simulate CDM events at chip level. A hierarchical approach associated with a novel CDM macromodel is developed to model a full-chip structure comprising several functional subsystems and multiple supplies. Full-chip CDM simulation enables the analysis of chip-level failure mechanisms and reliability of gate oxide. Simulation results on a CMOS ASIC chip processed in a 0.25-μm technology show high correlation with the measurement data.; The design of on-chip ESD protection has become increasingly critical and difficult because of shrinking device feature sizes, high operating speed, and system-on-a-chip (SoC) environment. A complex ESD protection network can be easily exposed during normal operation and can cause the degradation of internal circuit performance. The ESD noise, defined as the loss introduced by ESD stress and protection network, can be caused by three mechanisms: I/O protection induced signal loss, mixed-signal coupling through power protection circuits, and latent damage. In this work, we have presented the characterization of the ESD noise. The effect of the ESD protection network on the noise performance of sensitive circuits is investigated with a test chip processed in a 0.18-μm CMOS technology. Experimental results demonstrate a critical relationship between ESD reliability and power/ground (PG) coupling: ESD robustness and PG coupling are conflicting design goals. We have presented a novel noise-aware design technique for superior noise margin and improved ESD reliability. The use of hierarchical electrostatic discharge (HED) provides a low impedance discharge path for any ESD event. The estimation of maximum PG voltage in digital circuits is critical to determine an optimal topology of protection circuits subject to noise constraints. Experimental results demonstrate the effectiveness of this method.