| This dissertation focuses on low-power and high-performance VLSI circuit design issues. The research spans over different levels of VLSI design from the microarchitectural down to the circuit levels. Glitches are unnecessary sources of power consumption in the combinational logic. With hidden latch insertion, the glitching activity can be significantly reduced because the effective logic depth is reduced. However, the clock period or the pipeline stages remain the same. These latches, called fresh start latches, thus reduce power consumption in combinational logic significantly by reducing the active switching capacitance load. The measured power savings of the fabricated circuit is between 13% and 30%. Power optimization can also be done by exploring the data driven characteristics of programs. If computation executions can be bypassed based on previous computations, power reduction can be achieved. The microarchitectural feature execution cache achieves power savings of up to 60% per instruction. In addition, by reducing execution activity, the instruction per cycle for the data path can be improved by 15% to 45%. Last but not least, the reduction of substrate noise can improve signal integrity and reduce circuit leakage at the same time. The dual guard band filter described in this thesis actively fights noise in the substrate and reduces noise by 85% in post layout simulation. |
