Advanced gate dielectric for ULSI applications

Development and study of ultra-thin Jet-Vapor-Deposited (JVD) silicon nitride as an advanced gate dielectric for viable replacement of thermal oxide-gate in future generations of Ultra-Large-Scale-Integration (ULSI) devices are at the foci of this thesis. The primary objectives of this work are: to develop JVD processes to deposit high-quality silicon nitride films, to fabricate and thoroughly characterize the Metal-Nitride-Semiconductor (MNS) devices with JVD nitride-gate, and to study their reliability and hot-carrier properties.; Silicon nitride is being considered as a promising candidate to replace thermal oxide gate dielectric, as the later is reaching its scaling limit due to the excessive increase in gate tunneling leakage current. A novel technique, called the Jet Vapor Deposition (JVD), had shown promise to synthesize gate-quality silicon nitride films at room temperature while maintaining their obvious advantages of higher dielectric constants and strong resistance to impurity penetration. Thus, this thesis initially focuses on the optimization of JVD process parameters and development of various post-deposition treatments to achieve high-quality JVD nitride films. The physical properties of optimized JVD nitride films show significant nitrogen and negligible hydrogen contents. Compared to standard MOS devices, the MNS devices made with JVD silicon nitride gate exhibit much lower gate leakage currents, excellent interface and bulk electrical properties, and strong boron penetration resistance. The N- and P- channel MNSFET's fabricated with JVD nitride as the gate dielectric show competitive performance against those of their MOSFET counterparts. The MNS devices have been found to contain high densities of border traps. Experimental evidence presented in this dissertation suggests that the border traps may be the origin of the anomalous shape of the transconductance versus gate voltage curves of the nitridegate devices. The reliability evaluation of MNS devices made with ultra-thin JVD nitride-gate exhibit high breakdown strengths, negligible stress-induced leakage currents after stressing at high-fields, and very little trap generation. Allowable operating electric fields of more than 9 MV/cm at room temperature and more than 7 MV/cm. at 150°C for a 10-year projected lifetime have also been demonstrated on MNS devices. The Channel-Hot-Carrier (CHC) gate currents in MNSFET's show higher injection of electrons and holes due to lower electron and hole barrier heights at the Si-silicon nitride interface. Compared to their MOSFET counterparts, the hot-carrier stressing analysis on MNSFETs showed similar degradations in their performance. Potential application of JVD silicon nitride film to extend the scaling limit of tunnel oxide in the flash memory device is also demonstrated in this thesis. Lower gate leakage currents, coupled with negligible stress-induced leakage currents, in JVD nitride films have suggested a possibility to increase the data-retention time. High injection efficiencies of electrons and holes at low bias voltages in MNSFST's also showed promise to achieve higher programming speed of flash devices.