On-chip spatial image processing with CMOS active pixel sensors

Output images from the sensors more likely are not optimal results for display or further processing mainly because of noise, blurriness and poor contrast. In order to prevent these problems, image processors typically accompany the image sensors as a part of the whole camera system. Typically, two separated chips for sensing and processing are integrated onto the same printed circuit board connected by printed wires. The integration of image sensors and processing circuits on a single monolithic chip, called smart sensing, is done to obtain better performance from sensors and make the sensing and processing system more compact. It has become a popular idea. The integration of image acquisition and processing on the same focal plane has potential advantages through low fabrication cost, low power, compact size, and fast processing frequency. Noise and cross-talk can also be reduced through monolithic connections instead of off-chip wires, which are the only transfer medium between two separated chips.; In this thesis, we propose system-level architectures and design methodology for integrating image processing with CMOS active pixel sensors on a single chip. Conventional approaches to the integration categorized by circuit density of processing elements are not sufficient to achieve optimal design with power, speed, cost, and processing frequency. This thesis observes the nature of image processing algorithms and categorizes them in order to find out adequate design architecture for real time smart sensing. The algorithms can be divided in terms of signal type, operational domain, and regions of operation. We narrow these down into analog/low bit digital operation in spatial domain, and then subdivide the algorithms into point, local, and global operational regions. For each region of operation, we look at examples of processing algorithms and then subdivide them again according to on-chip implementation methodology. Here, we propose system-level architecture and on-chip design methodology for these categorized algorithms.; Four prototype chips, in this thesis, were designed and fabricated for the demonstration of smart sensing: One is a multi-camera system which is the inspiration for the smart sensing research, and the other three are demonstration imagers for each region of operation: point, local and global. These prototype chips are 64 x 64 photodiode arrays with on-chip image processing fabricated in standard 0.35 μm CMOS technology with 3.3V power supply. Each chip contains different functional processing and operates at different performances. We have successfully tested the chips with different testing performances and characteristics.; This thesis reports implementation architectures and design methodologies of on-chip processing with image sensors, its analysis along with operational performance and experimental results. These implementations demonstrate the advantages of the single chip solution and contribute as a milestone so designers and researchers can have a better understanding of smart sensing.