| On-chip signal extraction and characterization structures are slowly becoming a necessary component of any complex integrated circuit design. The increased integration of the modern System On a Chip has necessitated the development of these alternate test strategies to address the issue of device node access and signal integrity. The process of extracting a signal in an analog form across a chip boundary can often compromise its true nature, as these new systems stretch performance limits.;The aim of this thesis is to introduce two circuits for on-chip sub-nanosecond signal capture. The emphasis is placed on providing gigahertz rate effective sampling resolutions to provide a progressive characterization solution for the ever increasing operating speed of integrated circuits.;The first circuit presented is a hardware implementation of an undersampling algorithm that extends the operation of a pre-existing mixed-signal test-core to the capture of periodic signals with a bandwidth much greater than the sample rate of the system. This hardware unit comprises of a specialized timing module based on a Delay Locked Loop with tap selection circuitry. The effective sampling resolution of the system is limited by the intrinsic gate delay of the technology the timing module is implemented in.;The second circuit presented is a specialized jitter measurement device. This device is based on a Vernier Delay Line Time-to-Digital converter, and can provide resolutions well below a gate delay. Special emphasis was given to jitter measurement, since it is an issue that is often difficult to address adequately in the testing of many complex circuits. Both the aforementioned circuits were implemented in a 0.35 mum CMOS process, and results demonstrating their successful operation are presented. |
