Semi-reconfigurable data-path: Design and verification

A number of reconfigurable architectures have been developed in the past decade. For certain applications, such architectures can deliver a higher performance with “on-demand” formation of necessary hardware functions. However, existing reconfigurable architectures are not suitable for efficiently implementing complex data-path-intensive applications.; This study presents a semi-reconfigurable architecture, which is a mixed design of dedicated hardware modules and finegrain FPGA-like glue-logic resources. This semi-reconfigurable architecture can be employed to implement complex data-path components with reasonable performance and versatility. A case study of floating-point unit and MMX unit is described in this thesis.; The semi-reconfigurable data-path consists of two types of building blocks: custom-optimized components, which are mainly complex arithmetic primitives; and an FPGA-like structure, which provides programmable hardware resources to implement glue logic and other non-timing-critical components. Hence the hardware design is also divided into two steps. The first step is to optimize the dedicated hardware modules. A design fusion takes place where similar components of two functional units are identified, repartitioned, scrutinized, and redesigned. This process yields a set of new components that minimize overall circuit area and power consumption. These components can now serve both functional units through reconfiguration. The second step is then to design FPGA-like reconfiguring structure that adjoins these two functional units together. A goal is to reduce the performance loss due to an enhanced versatility associated with reconfigurable structures.; Implementation of such design is very complicated. The verification process hence becomes extremely difficult. Two approaches to accelerate this verification process are presented in this thesis. The first approach is code-perturbation simulation that uses application programs as test inputs. The approach perturbs the program-control-flow during simulation to exhaust all branching possibilities in a verification program. High simulation coverage can be achieved in a much shorter time using this approach. The second one is Si-Emulation system-level verification framework wherein the speed of hard-wired (FPGA-based) emulation is combined with the observability and controllability of gate-level simulation. A check-point method is employed to integrate emulation and simulation. Different sampling techniques are employed to reduce the resource requirements related to error detection while maintaining a high detection rate.