| In high-speed and high-throughput packet switches, system reliability is critical to avoid loss of a huge amount of information and to avoid re-transmission of traffic (or triggering some other means of data recovery). In this thesis, a series of concurrent fault-detection mechanisms for a multiple-plane crossbar-based packet switch is proposed. The switch model, called m + z model, has m active planes and z spare planes. This switch has distributed arbiters on each plane. The proposed detection scheme is able to detect a single fault in one time slot without increasing transmission overhead.; Considerable research has been done to propose efficient maximal matching schemes. Many of proposed scheduling schemes with a high performance are difficult or impossible to implement with the state-of-art technologies because the need of timing to accomplish a matched set of input and output ports.; An innovative Pipeline-based Maximal-sized Matching scheduling approach, called PMM, dramatically relaxes the timing constraint for arbitration with a maximal matching scheme. PMM preserves 100% throughput under uniform traffic and fairness for best-effort traffic as the pre-existing selected algorithm.; A new switch architecture that uses a round-robin scheme for input and output arbitration reducing the limitation of using a maximal matching scheme and providing a high performance is proposed. We propose a novel architecture: a Combined Input-One-cell-Crosspoint Buffer crossbar (CIXB-1). We show that the proposed architecture can provide 100% throughput under uniform traffic. A CIXB-1 offers several advantages for a feasible implementation such as scalability and timing relaxation.; A Combined Input-Crosspoint-Output Buffered (CIXOB-k) switch is described. This architecture inherits the properties of CIXB- k. However, CIXB-k does not offer 100% throughput for non-uniform traffic. It is shown that a very small speedup is sufficient to provide 100% throughput even when k is small. Also, a solution for relaxing the crosspoint memory amount and for scalability for a switch with a large number of ports is presented. |
