| The U-shaped, trench-gated, power metal-oxide-silicon field-effect transistor (UMOSFET) has very recently attracted attention as one of the most promising devices for low-voltage power management. The research reported in this thesis is part of a comprehensive effort undertaken jointly by the Pennsylvania State University and Fairchild Semiconductor Incorporated to develop high efficiency UMOSFETs. The performance and reliability of the UMOSFETs are analyzed in terms of processing and design. The processing parameter space included trench etching, trench sidewall preparation, gate dielectric composition and growth, and polycrystalline silicon deposition and doping. The design parameter space, on the other hand, included discrete device geometry, multi-device cell architecture, and doping level in different device regions. Using electrical characterization on especially designed UMOSFET test structures coupled with simplified device characteristics models, this study provides criteria for choosing design options and processing conditions that yield optimum output. It is shown that the UMOSFET's reliability is primarily affected by the gate oxide edge adjacent to the drain and the oxide/silicon interface overlapping the drain at the trench bottom corners. Positive charge buildup therein, induced by the stress, are observed to give rise to shorter effective channel length and, consequently, lead to oxide breakdown. Moreover, this thesis presents the first application of the deep level transient spectroscopy and charge pumping techniques to the study of charge trapping at the interfaces of gate dielectrics with sidewalls and bases of vertical trenches in silicon. |
