Fault tolerance and yield improvement of embedded memories

Recent advances in microelectronics industry allow us to create a System-On-Chip. The embedded memory is one of the vital parts of any system-on-chip. Today it is not enough just to design and fabricate the embedded memory. In order to put the System-On-Chip in mass production, the designer has to be concerned about yield and reliability of the embedded memory. This thesis provides background on fault tolerance improvement theory, and gives several new solutions on how to improve reliability and enhance yield of the embedded memory in efficient ways.;A complete fast embedded SRAM and Control Block for Programmable Clock Manager have been designed, implemented, integrated into a System-On-Chip and tested. The thesis incorporates two novel circuits that significantly improve embedded memory yield and reliability.;This thesis describes new embedded memory architecture for enhanced yield, performance and power consumption. The architecture is able to tolerate major defects including memory kill defects. The mathematical model of the new architecture is presented as well and shows the advantages of new architecture. The new induced Error-Correcting Code (ECC) for Multilevel Dynamic Random Access Memory (MLDRAM) is introduced. The ECC is able to correct 2-bit error and detect 4-bit error. The new ECC also improves reliability and power consumption of the embedded MLDRAM.