| This thesis details the design procedure of a CMOS power amplifier suitable for 2.4GHz Bluetooth application. In this thesis, several design techniques were introduced to overcome the design difficulties posed by the CMOS limitations and the nonlinear behavior of power amplifier. Before designing this PA, several traditional methods of PA implementation were investigated. After comparisons, a three-stage Class-E topology was chosen for its high efficiency and low sensitivity. While in this topology, many trade-offs exist among the design parameters, to get the optimal design, simulated annealing optimization technique is used for searching the global optimum. To incorporate the frequency dependent components in the optimization procedure, a simplified frequency domain method was also proposed to do the simulation. At last, a fully differential three-stage Class-E power amplifier was designed in a 0.18 um standard CMOS process and the simulation shows this power amplifier is able to deliver the power of 100mW to a 50O load with the power added efficiency of 61%. |
