Research On Key Technologies Of Self-Powered Low-Power CMOS Receivers For IoT Applications

With the rapid expansion of equipment scale in recent years,Internet of Things(IoT)equipment urgently needs to overcome challenges such as ecological fragmentation,limited transmission distance,and increased demand for low power consumption.Low-power IoT equipment is widely used in applications such as home/building automation,remote control,tag reading and writing,wireless sensing,and smart metering due to its low power consumption,low cost,large equipment scale,and low data rate requirements.To solve these issues,this thesis conducts research on low-power,high-performance configurable RF receivers in sub-GHz ISM/SRD frequency bands for low data rate applications,as well as RF energy harvesters for powering transceivers.Furthermore,this paper investigates and optimizes variable gain amplifiers(VGAs)and automatic gain control(AGC)circuits utilized in conventional receivers.The designs mentioned above are fabricated in standard CMOS technologies and verified through measurements.The main work and innovations of this thesis are as follows.(1)Based on multi-standard,low power consumption,and low cost requirements,lowpower dB-linear VGAs with large gain control range are studied.Two different chips are designed and implemented.a)The reason for the traditional VGA’ s limited gain adjustment range is investigated,and a VGA with high precision dB linearity and low power consumption is designed.To minimize the dB-linear transmission path while optimizing power consumption,dB-linear accuracy,and dB-linear adjustment range,a novel and simplified dB-linear gain control circuit is designed and co-designed with the VGA cell.This design is implemented in standard 55-nm CMOS process for tape-out verification,achieving a large gain control range of 62.4 dB with a dB-linear error of only ±0.4 dB.In addition,the power consumption is only 0.96 mW at a constant bandwidth of 80 MHz.The core area is only 0.011 mm~2.b)A design of a high PVT stable VGA with configurable bandwidth and automatic gain control is realized.A dual-mode gain adjustment technique is proposed to overcome the original design’s limitations on maximum gain and gain adjustment range,achieving a gain adjustment range of 68.2 dB and further optimizing the stability on process and power supply voltage.Besides,this design introduces gain-independent configurable bandwidth to adapt to data rates under different standards and enable power optimization.Fabricated in a standard 55-nm CMOS technology,the AGC achieves a constant output amplitude under an input swing of 40～110 mV.With a configurable bandwidth of 80～140 MHz,the AGC shows an adjustable power consumption range of 2.95～4.49 mW.The core area is only 0.026 mm~2.(2)Based on the requirements of low power consumption,high sensitivity,and wide-range configurability,a low-power,low-noise sub-GHz low-IF RF receiver is designed and implemented.Firstly,an improved parallel negative feedback low-noise amplifier is implemented.Based on current-reuse technique and subthreshold characteristics,low power consumption and narrow-band matching are realized,and noise optimization is realized within the range of configurable gain.Secondly,an IQ dual-channel passive mixer and a transimpedance amplifier(TIA)are implemented.By using a class-AB operational amplifier and GBW compensation resistors,the power consumption of the TIA is optimized.Finally,a gain-programmable complex filter is implemented to reduce power consumption of the circuits in the intermediate frequency part.GBW compensation resistors are used in the filter to further reduce power consumption.Besides,this filter provides image rejection,programmable gain and bandwidth,and bandwidth calibration function.This receiver is fabricated in a standard 0.13-μm CMOS technology.The measured receiver gain is-16～90 dB with 6 dB gain steps.The image rejection rate is larger than 37.1 dB in the overall gain range.The noise figure is only 2.1 dB at 433 MHz.This receiver consumes only 3.63 mW at 1.2 V supply voltage and has a core area of 2.3 mm~2.(3)Based on the design challenges of low power consumption,low cost,and long-distance transmission of low-power IoT equipment,a fully integrated 2.4 GHz RF energy harvester with optimized sensitivity is designed.By analyzing differential cross-coupled rectifiers suitable for high sensitivity applications,an improved cross-coupled rectifier is proposed.By designing a gate-voltage boost circuit with an optimized threshold voltage,this improved rectifier shows an optimized sensitivity.Besides,a diode-connected single-sided bias circuit is introduced to suppress the reverse leakage current,thus improving efficiency.In addition,a power management unit(PMU)is designed to address the effects of abrupt changes in input ambient power on the efficiency of energy harvesting.Combined with PMU,two fully integrated energy harvesting systems are designed based on two different rectifiers.The designs achieve on-chip matching and are optimized based on packaging.Fabricated in a standard 40-nm CMOS technology,the chip has a sensitivity of-14.8 dBm at 400 mV output voltage and a peak efficiency of 18.2%.