| The motivation of this thesis was to develop new built-in self-test schemes for analog, digital and mixed signal devices, to reduce the time to market of defect-free circuits, thus reducing testing costs, and have the proposed test schemes be compatible with the IEEE 1149.4 Mixed-Signal Test Bus Standard. Reducing the time to market, aids in the reduction of half the cost for an analog device and reduces one third of the budget for mixed signal devices. The test schemes presented can be divided in to two main categories. (1) Quiescent Nodal Voltage Test. A novel built-in self-test scheme designed for preliminary testing of analog circuits is presented. This scheme is denoted as VDDQ. It is an on chip solution to a common technique used by analog designers; measuring the quiescent nodal voltage of a circuit under test to determines if the circuit is operational. The circuit requires no allocation of pins for inputs or outputs of the test circuitry. The VDDQ testing scheme performs at a speed that is twelve times faster than the reported industry standard. (2) High Speed Dynamic Current Sensor: Supply currents give global information on digital and analog VLSI circuits. The static or quiescent current determines biasing currents on analog and leakage currents in digital circuits. These currents are footprints for defect-free circuits. By detecting deviations from the expected current waveforms, defective circuits are removed from the test line at an early stage, thus reducing test cost. Two different schemes to measure dynamic currents are presented. Both schemes have a gain bandwidth product on the order of 10 GHz. The first scheme presented uses a folded cascode OTA, with a single supply of 2.7V. The second current sensor presented takes advantage of a recently reported cell called Flipped Voltage Follower. This scheme senses fast dynamic currents using a single supply of 1.8 Volts. Analysis simulation and experimental results are discussed for the validation of all proposed schemes. |
