| The progress in CMOS (Complementary Metal Oxide Semiconductor) technology has entered the nano-micron realm, but its constant scaling have made these circuits more susceptible to noise disturbances such as single event (SE) particle induced transient pulses.;With today's deep sub-micron design technology, reliability is becoming a major concern as radiation-induced issues which were usually faced by circuits used for space applications, are now also applicable to those used at terrestrial level. Scaling has not only affected device dimensions but also parametric aspects like operating voltages, node capacitances and drive currents which have also been lowered. This has affected the sensitivity of circuits thereby making them more vulnerable to radiation strikes. As operating speeds have soared, designers today also have to address the vital issue of increasing power consumption wherein the leakage power component is on the rise. Subsequently, several attempts have been made to downgrade the influence of consumed energy at circuit level.;While introducing new circuit design styles to optimize power consumption, circuit designers have to be conscious of the fact that SE robustness can be different for different design styles and therefore it has to be taken into consideration. This especially becomes pivotal for critical applications like life support systems and implantable medical devices where reliability and performance are the most important objectives over cost. Hence this study discusses the radiation tolerance of various low power design techniques like the LECTOR (Leakage Controlled Transistor), SCCMOS (Super Cutoff CMOS), the SC-LECTOR (SCCMOS combined along with LECTOR), and finally DTMOS (Dynamic Threshold CMOS). The simulations are performed at 45nm process technology with a supply voltage of 0.6V and are verified using HSpice and predictive (PTM) model. The results indicate that the SCCMOS style is more tolerant to radiation strikes among all styles considered, as it provides a higher critical charge due to better current drive as compared to conventional CMOS. It also provides better critical delay charge which is approximately 1.75 times better than conventional CMOS. |
