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RF CMOS class C power amplifiers for wireless communications

Posted on:2002-02-15Degree:Ph.DType:Thesis
University:University of California, BerkeleyCandidate:Narayanaswami, Ramakrishna SekharFull Text:PDF
GTID:2468390011490896Subject:Engineering
Abstract/Summary:
Recent efforts in the design of integrated circuits for RF communication transceivers have focussed on achieving higher levels of integration by including more and more analog functional blocks onto a single silicon CMOS chip. One of the final blocks that has yet to be successfully integrated is the Power Amplifier (PA). The PA is the final functional block in the transmit path; its function is to amplify the signal to be transmitted to the required transmit power level. In general, PAs are difficult to integrate in CMOS because of technology limitations that severely limit the efficiency of the PA.; This thesis describes theoretical analysis and circuit techniques for the design and implementation of RF Class C PAs in CMOS technologies. To date, very few methods exist for designing Class C PAs; in the past, much of the design process has been empirical. The theoretical work in this thesis attempts to describe a method for designing a Class C PA in CMOS without resorting to blind use of a circuit simulator. Using fourier series analysis, the drain current waveform of a CMOS Class C PA (which is dependent both on the input and output voltage waveforms) is determined to first-order in order to generate an approximate solution to the design goal before a circuit analysis tool is required, Circuit techniques used to combat the technology limitations imposed by CMOS technologies include the use of differential circuits in the signal path, cascoded stages and a modified tuning method which allowed for the use of extremely large output devices but not requiring passive devices that were not feasible in a CMOS technology.; A 1.75-GHz, 1.7W CMOS PA was designed in an STMicroelectronics 0.35-μm, five-metal doubly-poly CMOS process and implemented both as a stand-alone chip and as part of a fully-integrated transmitter chip. In simulation, the peak efficiency of the PA was 40%. Due to an over-estimation of the quality factors of the on-chip spiral inductors used in the design, the evaluation of the PA revealed a peak power of just over 1-W and a peak efficiency of 27%. The PA did meet the spectral mask requirements of the DCS 1800 cellular communications system for which it was designed, and comparison of the PA output of the integrated version indicated that the PA amplified the desired signal without too much degradation of the signal.
Keywords/Search Tags:CMOS, Class, Power, Integrated, Signal, Circuit
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