| System-in-a-Package (SiP), a generalization of System-on-a-Chip (SoC), provides a cost-effective solution for large-scale memory and logic integration and an attractive alternative for embedded memory. SiP overcomes formidable integration barriers without compromising individually optimized chip technologies. By preserving on-chip electrical environment, SiP matches or exceeds SoC performance with lower cost. This thesis presents a comprehensive analysis of system-in-a-package implementation platform, including SiP processing technologies, SiP design methodology, electrical and thermal modeling of SiP package, and a model of memory access time inside SiP module. Innovative configurable area-IO memory architecture for SiP, which enables one generic memory to meet the bandwidth requirements of different applications, is also discussed in this thesis. Two design cases, large-scale FPGA and DRAM integration and configurable area-IO SRAM, have been described to validate our approach. It is demonstrated that system-in-a-package will have tremendous opportunities in future system-level integration. |
