Synthesis of a parameterizable complex mixer for digital radio receivers targeting FPGAs

Wireless communication systems have evolved during the last two decades from the first generation FDMA, to TDMA, and lately CDMA. As one major component in the communication system, the digital receiver is usually designed as a dedicated circuit for a specific communication standard. Such design is not suitable for the applications that require the dynamic allocation of channel bandwidth and multiple carriers. One approach to solve the problem is to design the system using configurable, scalable and parameterizable components.; A digital complex mixer is a major component of a digital receiver. It performs the frequency translation to recover the channel information from the modulated IF signal. This thesis focuses on the design of a scalable, parameterizable complex mixer targeting FPGAs.; The functional blocks of the complex mixer include a Baugh-Wooley-Adder-Tree based complex multiplier, and a Linear Segment Interpolation based Direct Digital Frequency Synthesizer (DDFS). Both of the complex multiplier and the DDFS are pipelined to achieve higher performance. The system is scalable, and accepts the user specified parameters through a command line interface. The system is implemented on a Xilinx VirtexE FPGA device. The speed of the pipelined system exceeds 150 MHz using a 12-bit complex multiplier and an 8-segment DDFS. The system is verified at the RTL level, the post-synthesis level and the board level to ensure that the design can perform the desired functionality.