Adaptive reference generation for 1T1C ferroelectric memories

This thesis presents the design of a complete 1T1C ferroelectric memory testchip using an adaptive reference generation scheme and a time-reference read scheme. The adaptive reference generation scheme tracks the fatigue of the ferroelectric capacitors and provides equal sensing margins throughout the lifetime of the memory. The time-reference read scheme detects data based on the signal timing rather than on the voltage level. This allows for an implementation of the adaptive reference generation scheme using techniques similar to those used in timing recovery circuits.; To verify the effectiveness of the adaptive reference generation scheme, a 32kbit 1T1C Ferroelectric Random Access Memory (FeRAM) testchip has been designed in a 0.18μm CMOS process with a 0.35μm ferroelectric process using planar capacitors.