Architecture of a pipelined closed-loop gigabit bit error detector

A circuit architecture is presented for a Bit Error Detector utilizing deep pipelining and parallelism to achieve aggregate throughput in the gigahertz range. The architecture is not limited to pseudo random bit sequences, but is designed to accept any arbitrary data stream regardless of bit transition density. The pipeline performs a correlation and alignment between the arbitrary reference bit stream and its delayed bit stream returning from a system under test. The task then switches to the detection of bit errors induced in the system, and are accumulated to calculate the bit error rate. A bias in the bit error rate is determined by the separation of errors into ones errors and zeroes errors. The pipeline performs both correlation and bit error detection under ground-based conditions with constant propagation delay, or under conditions prone to propagation delay fluctuations arising from the varying range of a satellite in geostationary orbit.