Testing analysis of BiCMOS circuits

With the anticipated growth of Bicmos technology for high performance ASIC design, the issue of testing takes on great significance. The development of mixed bipolar and CMOS technology aims to combine the best of bipolar high current capability and speed, CMOS low power and high density. This research emphasized on the testing of different adder logic families for various stuck-open and stuck-at faults using stuck-at, quiescent current (Iddq) and delay fault testing.; A stuck-open fault is modeled by connecting a 10 Mega ohm resistance between the device's terminal and one of the nodes. A stuck-at or bridging fault is modeled as a resistive connection between two terminals of the transistor.; The detection of different open and short faults with respect to stuck-at, quiescent current (Iddq), and delay testing is investigated using circuit level simulation on four different Bicmos logic families. The proposed adder circuits are simulated using Pspice (1.5μprocess).