Design And Simulation Of High-Speed, Low-Power BICMOS Memory

The performance of computer has developed rapidly since the advent of the computer for fifty years and especially the technology of the CPU has advanced much faster. However, the development of the computer's memory lays behind the development of CPU. It effect's the computer's performance badly .So it brings forward higher request to the memory including qualifications of high-integration density, low-power and high-speed.BiCMOS (Bipolar Complementary Metal-Oxide-Semiconductor) technology combines bipolar device with CMOS device effectively, so it not only holds CMOS circuit's virtues of low power, high integration density, but also obtain bipolar circuit's merits of high speed strong driving power. So people are increasingly attaching much importance to the technology in recent years.The SRAM designed in this dissertation adapts advanced BiCMOS technology, Bank structure, CSEA memory cell and advanced encoding technology. It will improve the storage performance greatly. Finally, SRAM's partial unit circuits have been simulated again and again in this dissertation and the fall circuit has also been simulated by software. Simulation result shows that the designed SRAM's capacity cell has reached 1 M and its power consumption is 1.78W lower 3.3-power supply. Design objective is performed in high speed, high accuracy and low power as a whole.Accord to performance index in the SRAM circuit and existing technological level of IC, technological design points used to the SRAM are concisely proposed in this dissertation.