| Reconfigurable logic devices that are based on a Field Programmable Gate Array (FPGA) substrate are gaining widespread acceptance. As such devices are used in many different configurations, manufacturers need to ensure that each potential configuration will not fail due to device defects. This flexibility leads to severely increased test times, which in turn increase the semiconductor device's total cost. This thesis presents a method to speed up test and diagnosis times using reconfigurability. Furthermore, a scheme for the incorporation of the test architecture, which reduces test and diagnostic times of reconfigurable logic interconnects, is described. The test architecture includes added Feedback Shift Register (FSR) components that change the circuit configuration during testing but are completely transparent during the eventual customer's usage. Equally, algorithms are presented to produce test and-diagnosis configuration sets with a minimized number of configurations, along with the creation of an FSR that produces the test and diagnosis sets by dynamic reconfiguration of the device. |
