| In this thesis, various receiver architectures are reviewed and issues specific to direct-conversion receiver (DCR) design identified. The design of a DCR consisting of a low-noise amplifier and mixer is detailed. The DCR is targeted at the IEEE802.11 a wireless LAN standard, which specifies operation in the 5 GHz unlicensed national information infrastructure (UNI) band, and is fabricated in IBM's 0.5mum 50GHz BiCMOS technology with analog metal option. The receiver has a simulated and measured voltage conversion gain of 31 dB at 5.25 GHz. It has a simulated noise figure of 4.7 dB, IIP3 of -9 dBm, IIP2 of +42 dBm and draws 16.1 mA of current from a 2.75 V supply.;Differential-mode feedback is investigated as a method of reducing DC offset. Criteria for the differential-mode feedback loop (DMFL), including loop-gain, frequency response and output noise are identified. Three circuits to implement the DMFL are designed and simulated.;It is found that the ratio of the corrected to uncorrected differential DC output voltage, with the application of feedback, is equal to the inverse of the open-loop gain of the DMFL. As well, noise generated by the DMFL circuit is suppressed by the frequency-dependent open-loop gain, such that at frequencies outside of the DMFL frequency bandwidth, the DMFL output noise is not suppressed.;The following requirements for the DMFL are identified: (1) to have high loop gain at 0 Hz to reduce DC offset, (2) to have low loop gain at frequencies of desired information so the desired signal is not attenuated, (3) to have low output noise at frequencies of desired information where the noise suppression by the loop is reduced, and (4) to be fully integrated to take advantage of the higher levels of integration achievable with a DCR architecture. This research has resulted in an improved understanding of the application of feedback to mitigate DC offsets in direct-conversion receivers. |
