Research And Design Of A Direct-conversion Receiver For UHF RFID Readers

Radio-frequency identification(RFID) is the wireless use of electromagnetic fields to transfer data, for the purposes of automatically identifying. It is of great significance to do the research of the reader, as an important component of RFID system. The demand for higher data rate and longer communication range forces RFID researchers to focus on the UHF band.A highly integrated UHF RFID reader receiver IC design in 0.18μm CMOS process covering the entire 860 MHz to 960 MHz RFID band supporting the EPC global Class-1 Generation-2 standard is presented.The main research points of the paper include the analysis of communication protocals, the design and simulation of the circuits, and the layout verification of the whole system, summarized as follows.Direct-conversion architecture integrates a two-mode RF front-end and analog baseband is used for the receiver for a high level of integration and low power consumption. According to the analysis of protocol, the system specifications under complex environment are calculated, which provide the basis of circuit design.Depending on different needs of listen-before-talk(LBT) and talk mode, a two-mode I/Q RF front-end, consisting of a two-mode low noise amplifier(LNA) and I/Q downconverters, is presented. The front-end features a receiver with sensitivity of-77 dBm in listen-before-talk mode(LBT) mode and P1 dB of-2.1dBm in talk mode.The baseband containing lowpass filter(LPF), programmable gain amplifier(PGA) and DC-offset canceller(DCOC), is proposed to satisfy the different data rates. LPF with selectable cut-off frequencies from 0.48 MHz to 1.68 MHz helps to meet stringent requirement as specified by the protocol. The gain of the PGA in decibels changes linearly with a resolution of 1 dB and control range of 48 dB by switches. All the signal beyond 300 kHz will be attenuated 49 dB while the baseband signal will be amplified 5dB by the DCOC blocks.Based on SMIC 0.18μm CMOS 1P6 M process, the points in RF and analog circuits’ layout design are summarized. The whole layout of the receiver occupies a die area of 2.9mm×1.0mm including pads. It is proved, the post-simulation results satisfy the design specifications.