| This dissertation presents a fully integrated direct conversion receiver implemented in 0.18μm CMOS for wireless communication systems, especially 5-GHz UNII band applications. Direct conversion architecture merits significant advantages in both cost and power consumption but inherits many serious technical difficulties in flicker noise and DC offset. In this dissertation, complete and practical solutions are provided to resolve these issues. A unique receiver structure, including a single-balanced passive mixer and two special buffers, is created to reduce the flicker noise. Measured flat spot noise figure (<2 dB) is obtained over the complete baseband signal range (100 KHz–8.4 MHz). A new feedback mechanism is adopted specifically to minimize the DC-offset of the passive CMOS mixer with a measured 20 dBc DC rejection and 10 KHz cutoff frequency. Extensive theoretical analyses have also been conducted to provide the base of understanding and guide the CMOS circuit design in LNA, passive mixers and DC offset cancellation. |
