New methods for dynamic power estimation and optimization in VLSI circuits

This dissertation addresses the problem of dynamic power estimation and optimization in the design of digital CMOS VLSI circuits. A Petri net based technique is proposed for dynamic power estimation, while, economic models, game theoretic formulation and Nash equilibrium based solutions are investigated for power optimization during gate level and behavioral level tasks in the synthesis of low power high performance circuits.; A novel methodology based on Petri net modeling is presented for real delay switching activity and power estimation of CMOS circuits, considering both gate and interconnect delays. A new type of Petri net called Hierarchical Colored Hardware Petri net (HCHPN), which accurately captures the spatial and temporal correlations in modeling switching activity is described. While providing the same accuracy levels compared to existing simulators, the proposed strategy requires significantly less per-pattern simulation time.; The design and application of economic and game theory models for power optimization during behavioral and gate level synthesis is an important contribution of this dissertation research. Economic and game theoretic models have been applied to solve a few problem in traffic flow optimization in computer networking, and job shop scheduling and resource allocation problems in operations research. In this work, several VLSI design automation problems are represented as economic models which are transformed as game theoretic models and solved using the Nash equilibrium function. Game theoretic modeling allows the simultaneous optimization of multiple conflicting objectives which, for example are, delay, area and power parameters in the case of VLSI design. Several problems at the gate as well as behavioral level are explored for power optimization.; The synthesis problems investigated at the gate level are: gate sizing, buffer insertion, integrated gate sizing and buffer insertion, voltage scaling, and simultaneous gate sizing and voltage scaling. Several models and algorithms are developed for these problems, and implemented and tested using benchmark circuits. The proposed approaches yield significantly better optimization compared to integer linear programming based approaches, with comparable runtime and memory requirements. The behavioral synthesis problems of: scheduling, binding and combined scheduling and binding are formulated as auctions and solved using the game theoretic Nash equilibrium function. The proposed algorithms yield significantly better power reduction with no increase in area overhead and only a slight increase in latency for some of the benchmark circuits.