Low power encoding techniques for memory and video subsystems

This thesis presents low-power encoding techniques for off-chip buses in a portable battery-powered device, including Dynamic RAM (DRAM) address bus, video frame-buffer bus, UO bus, and video interface.; Power consumption of the DRAM address bus comprises a rather large portion of the total system power. Chapter 2 describes an irredundant encoding technique to minimize the switching activity on a multiplexed DRAM address bus. The graph-theoretic encoding technique reduces switching activity on the memory bus by a factor of two for a sequential access pattern.; The video controller consumes power by constantly generating memory transactions between the video frame-buffer and the video controller whenever the display is active. Chapter 3 reports a software-only encoding technique that uses the pixel translation mechanism of the video controller as a coding table and then reassigns the codes according to the image characteristics. Experimental results show power reduction reaches 29% for text-based and 17% for graphics-based images without any area/power/performance overhead at runtime.; The virtual memory and file system cause numerous transactions on the I/O bus between the main memory and the secondary Flash memory. Chapter 4 describes a software encoding technique that dynamically inverts the data on a page basis. Experimental results show that the transition count on the I/O bus can be reduced by 10--26%.; Chapter 5 presents a low-power encoding technique for a digital serial video interface. Based on the observation that the signal differences between adjacent pixels follow a Gaussian distribution, an optimal irredundant encoding is performed to minimize the transition counts on the video interface. Experimental results show up to a 75% transition reduction.; Chapter 6 presents a low power technique of concurrent brightness and contrast scaling (CBCS) for the backlight of a transmissive TFT-LCD display. A contrast-oriented metric is used to formulate and solve the optimal CBCS problem.; Chapter 7 concludes this thesis and provides future directions of power minimization problems for off-chip buses and digital video interfaces.