| With the developing of core number in processors,on-chip memory has become a challenge to improving computer performance continuously.For the emerging of “Power Wall” and “Memory Wall”,we need to optimize the storage and power consumption of memory system immediately.Nowadays,many researchers working on the enlargement of on-chip memory,but with the enhancement of performance,it is difficult to get a proper power consumption.In this paper,we focus on benchmark SPEC CPU 2000/2006,analyzing and concluding the features of the applications.Based on the result,proposing a dynamic power optimization method towards different applications.By discussing the access pattern of the applications in an interval time,get the most possible access positions.Thus,power-gating the circuits and migrating the data.The main works of this thesis is as following.1.Based on the relating works of 3D die-stacking,developing a monitor which relies on access trace and simulates the behavior of 3D DRAM Cache that utilizes a full system monitor and main memory monitor.Differing from the existing work,on this monitor,we use only benchmark trace to acquire performance parameter of the memory hierarchy.By analyzing the read/write process and throughout of 3D situation,our paper get good performance in Last Level Cache(LLC).The experiments show that,when 3D DRAM Cache is used as the Last Level Cache of the memory system.Read latency can be 1.82 X faster than baseline system,write latency can be 6.38 X faster than baseline system.Meanwhile,throughout can be 1.45 X compare to the baseline.2.By analyzing the access patterns of applications in SPEC CPU 2006,get the features of data access.In the beginning interval of time,it can be concluded that the future data would be more intent to which banks.Based on this simple predict,we could power off the bank and migrate data,therefore,saving energy.3.Proposing a method to do power management of 3D DRAM Cache.Our LLC power management can be divided into 5 steps.They are access pattern analyze,K-mean cluster,data migration,remapping and bank power-gating.In every 100 thousand ticks,it would retest the access pattern of the application,determine the close and open of each bank.From the result of light-weight statistic assessment and full system simulation,the leakage power consumption decreased in this 3D die-stacked system.Thus,in a LLC,we can acquire the improvement of performance,and decrease 28.57% of leakage power in average,even 62.5% decrease in 456.hmmer and 465.tonto. |
