Capacitance-voltage characteristics of silicon MOSFETs in the presence of gate tunneling

Abstract Reducing the gate-oxide thickness of MOS devices below 2 nm results in a significant gate current due to the quantum-mechanical tunneling of carriers through the gate dielectric. Experimental capacitance-voltage C(V) characteristics exhibit substantial reduction in both the inversion and accumulation capacitance measured in the presence of a large gate-tunneling current. The inversion and accumulation capacitance degradation greatly limits the usefulness of C(V) measurements in MOS device-parameter extraction. Current models of this capacitance behavior either cannot account for non-uniform channel characteristics caused by the tunneling current, or requires a large number of fitting parameters. In this thesis, a distributed-network model with few fitting parameters is developed and is helpful in providing device and characterization engineers insight into MOS C(V) characteristics in the presence of gate tunneling. This distributed-network model is based on MEDICI device simulations that account for the gate tunneling current. The static and small-signal lumped-element parameters are obtained from the static MEDICI simulation results. A circuit netlist based on the parameters extracted is then generated, then used as input to the circuit simulator HSPICE. The device small-signal characteristics are then simulated in HSPICE, and the capacitance components are extracted. Finally, simulation results with different device and operation parameters are presented. These results compare favorably with published experimental data. The results indicate that the equivalent-circuit approach can provide device and characterization engineers a general framework for predicting MOS C(V) characteristics in the presence of gate tunneling and an essential tool in the design of future MOS test structures.