Study On The Preparation And Properties Of Y₂O₃/Si MOS Capacitors

Si MOS devices are very important components of integrated circuits. With the continuous increase of the integration density, the feature size of the device is becoming smaller and smaller. The thickness of the traditional Si O₂ gate dielectric layer is close to the thickness of several atomic layers correspondingly, which will cause many problems, such as sharp increase of gate leakage current, decrease of reliability of the device. In this case, high-k materials instead of Si O₂ as gate dielectric layer become one of important solutions. Among the many high-k materials, Y₂O₃ is one of promising high-k materials for gate dielectric, which has a large band gap?⁵.6e V?, large dielectric constant?¹5?, stable chemical properties. What's more, it has large band offsets, good thermal stability and lattice matching with Si.substrate.In this thesis, 8 groups of different Y₂O₃/Si MOS capacitors were prepared on p type Si substrates by different growth and annealing conditions of Y₂O₃ films based on magnetron sputtering deposition. The thickness of the dielectric layer of each sample is about 9nm measured by spectroscopic ellipsometry. The results of the XPS analyses indicate that the Si element exists in parts or all chemical states of Si^*?Si¹⁺, Si³⁺, Si⁴⁺, the Y element mainly exists in the form of yttrium silicide, and the O element mainly exists in the chemical bond of Y-O-Si at the Y₂O₃/Si interface. Compared to the MOS capacitor that the Y₂O₃ dielectric layer was deposited at room temperature, the samples that the Y₂O₃ dielectric layers were deposited while the substrate is heated and the samples that the Y₂O₃ dielectric layers were annealed at high temperature, the diffusion between the Si atoms and the atoms of Y₂O₃ increases at the interface. The band alignment of Y₂O₃/Si is obtained based on XPS analyses, the results show that the conduction band offset ?Ec and the valence band offset ?Ev of Y₂O₃/Si are 2.7e V and 2.4e V respectively.The Y₂O₃/Si MOS capacitors were tested by C-V, I-V. The test results and further analyses show that, for the MOS capacitor that the Y₂O₃ dielectric layer was deposited at room temperature, its flat band voltage Vfb and hysteresis voltage Vhy are-3.07 V and 0.53 V respectively, indicating that the negative shift and the hysteresis of the C-V curve is large, which is mainly caused by the large fixed oxide charges Qf and the oxide trap charges Q_ot. On the other hand, the interface density is large and the dielectric constant of the dielectric layer is only 6.1. In general, the quality of the dielectric layer and the capacitance characteristics of this capacitor are not good. For the sample that the Y₂O₃ dielectric layer was deposited at room temperature introducing 4% oxygen in the deposition process, the flat band voltage Vfb negative shift and the hysteresis voltage Vhy are decreased by 0.53 V and 0.19 V respectively because of the decrease of the fixed oxide charges Qf and the oxide trap charges Q_ot, While the dielectric constant and the leakage characteristic is not improved. For the samples that the Y₂O₃ dielectric layers were deposited while the substrate is heated at 300?, 500?, the hysteresis voltage Vhy are reduced by 0.34 V and 0.45 V respectively, which indicates that the oxide trap charges Q_ot are deceased. Besides, the gate leakage current are obviously decreased. But the dielectric constant are 7.1 and 6.4 respectively, which are hardly improved. For the samples that the Y₂O₃ dielectric layers were annealed at 400?, 500?, 600?, the dielectric constant are 11.7, 10.1 and 10.7 respectively. The qualities of the dielectric layers and the capacitance characteristics of these capacitors are obviously improved. What's more, the fixed oxide charge density, the oxide trap charge density, the interface density and the gate leakage current decrease as the annealing temperature increases, which indicate that the Y₂O₃/Si MOS properties show more improvements as the annealing temperature increases.The mechanisms of gate leakage current of Y₂O₃/Si MOS capacitor are analyzed. When applied negative gate voltage, the leakage mechanisms in low, medium and high voltage range are Schottky emission, F-P emission and F-N tunneling, respectively. The voltage range for F-P emission is relatively large, which is caused by the oxide trap charges in the dielectric layer.